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1 semicustom products ut0.6 ? cr ?? commercial radhard tm gate array family data sheet may 2014 www.aeroflex.com/radhardasic features ? multiple gate array sizes up to 500,000 usable equivalent gates ? toggle rates up to 150 mhz ? advanced 0.6 ??? 0.5 ? l eff ?? radiation-tolerant silicon gate cmos processed in a commercial fab ? operating voltage of 5v and/or 3.3v ? qml class q & v compliant ? designed specifically for high reliability applications ? commercial radhard tm for radiation-tolerant to 300 krads(si) to meet space requi rements and seu-immune to less than 2.0e-10 errors/bit-day ? jtag (ieee 1149.1) boundary-scan supported ? low noise package technology for high speed circuits ? design support using mentor graphics? and synopsys tm in vhdl or verilog design languages on sun? and linux workstations ? supports cold sparing for power down applications ? supports voltage translation - 5v bus to 3.3v bus - 3.3v bus to 5v bus product description the high-performance ut0.6 ? crh gate array family features densities up to 500,000 equivalent gates and is avail- able in mil-prf-38535 qml q and v product assurance levels and is radiation-tolerant. the commercial radhard tm silicon is fabricated at on semi- conductor using a minimally invasive processing module, developed by aeroflex, that enhances the total dose radiation hardness of the field and gate oxides while maintaining circuit density and reliability. in addition, for both greater transient radiation-hardness and latchup immunity, the aeroflex 0.6 ? process is built on epitaxial substrate wafers. developed using aeroflex?s patented architectures, the ut0.6 ? crh gate array family uses a highly efficient continu- ous column transistor archit ecture for the internal cell construction. co mbined with state-of -the-art placement and routing tools, the utilization of available transistors is maxi- mized using three levels of metal interconnect. the ut0.6 ? crh family of gate arrays is supported by an ex- tensive cell library that includes ssi, msi, and 54xx equivalent functions, as well as configurab le ram and cores. aeroflex?s core library includes the following functions: ? intel 80c31? equivalent ? intel 80c196? equivalent ? mil-std-1553 functions (brctm, rti, rtmp) ? mil-std-1750 microprocessor ? risc microcontroller ? configurable ra m (sram, dpsram) ? usart (82c51) ? edac ? aeroflex gaisler we offer aeroflex gaisler leon3 and other ip which can be reviewed at www.gaisler.com/cms
2 table 1. gate densities notes: 1. based on nand2 equivalents. actual usable gate count is design-dependent. estimates reflect a mix of functions including ram. 2. includes five pins that may or may not be reserved for jtag boundary-scan, depending on user requirements. 3. reserved for dedicated v dd /v ss and v ddq /v ssq . 4.aeroflex offers four die sizes: kd (280 mils), kc (407 mils), kb (535 mils), and km (677 mils) . low-noise device and package solutions the ut0.6 ? crh array family?s output drivers feature program- mable slew rate control for minimizing noise and switching transients. this feature allows the user to optimize edge charac- teristics to match system requirements. separate on-chip power and ground buses are provided for in ternal cells and output drivers which further isolate internal design circuitry from switching noise. in addition, aeroflex offers a dvanced low-noise package tech- nology with multi-layer, co-fired ceramic construction featuring built-in isolated power and ground planes (see table 2). these planes provide lower overall re sistance/inductance through pow- er and ground paths which minimize voltage drops during periods of heavy switching. thes e isolated planes also help sustain supply voltage during dose rate events , thus preventing rail span collapse. flatpacks are available with up to 352 leads; pgas are available with up to 299 pins and lgas to 472 pins. aeroflex?s flatpacks feature a non-conductive tie bar that helps maintain lead integrity through test and handling operations. in addition to the packages listed in table 2, aeroflex of fers custom pack age development and package tooling modification services for individual requirements. device part numbers equivalent usable gates 1 signal i/o 2 power & ground pads 3 ut06mra010 10,000 192 48 ut06mra025 25,000 192 48 ut06mra050 50,000 192 48 ut06mra075 75,000 312 72 ut06mra100 100,000 312 72 ut06mra150 150,000 312 72 ut06mra200 200,000 432 96 ut06mra250 250,000 432 96 ut06mra300 300,000 432 96 ut06mra350 350,000 432 96 ut06mra400 400,000 544 144 ut06mra450 450,000 544 144 UT06MRA500 500,000 544 144
3 table 2. packages notes: 1. the number of device i/o pads available ma y be restricted by the selected package. 2. pga packages have one additio nal non-connected index pin (i.e., 84 + 1 index pin = 85 total package pins for the 85 pga). contact aeroflex for specific package drawings. package type/ leadcount 1 025 050 075 100 150 200 250 300 350 400 450 500 550 600 flatpack 84 x x 132 x x 172 x x x x x x 196 x x x x x x 208 x x 256 x x x x x x x x x x x x 304 x x x x 352 x x x x x pga 2 299 x x x x lga 472 x x x x x
4 extensive cell library the ut0.6 ? crh family of gate arrays is supported by an exten- sive cell library that includes ssi, msi, and 54xx-equivalent functions, as well as ram and other library functions. user-se- lectable options for cell confi gurations includ e scan for all register elements, as well as output drive strength. aeroflex?s core library includes the following functions: ? intel? 80c31 equivalent ? intel? 80c196 equivalent ? mil-std-1553 functions (rti) ? mil-std-1750 microprocessor ? standard microprocessor peripheral functions ? configurable ram (sram, dpsram) ? risc microcontroller ? usart (82c51) ? edac ? aeroflx gaisler ip refer to aeroflex?s ut0.6 ? crh design manual for complete cell listing and details. i/o buffers the ut0.6 ? crh gate array family offers up to 544 signal i/o locations (note: device signal i/o av ailability is af fected by pack- age selection and pinout.) the i/o cells can be configured by the user to serve as input, output, bidi rectional, three-state, or addi- tional power and ground pads. output drive options range from 2 to 12ma. to drive larger off-chip loads, output drivers may be combined in parallel to provide additional drive up to 24ma. other i/o buffer features and options include: ? slew rate control ? pull-up and pull-down resistors ? ttl, cmos, and schmitt levels ? cold sparing ? voltage translation - 5v bus to 3.3v bus - 3.3v bus to 5v bus jtag boundary-scan the ut0.6 ? crh arrays provide for a test access port and bound- ary-scan that conforms to the ieee standard 1149.1 (jtag). some of the benefits of this capability are: ? easy test of complex assembled printed circuit boards ? gain access to and control of internal scan paths ? initiation of built-in self test clock driver distribution aeroflex design tools provide methods for balanced clock distri- bution that maximize drive capability and minimize relative clock skew between clocked devices. speed and performance aeroflex specializes in high-performance circuits designed to op- erate in harsh military and radiation environments. table 3 presents a sampling of typical cell delays. note that the propagation delay for a cmos device is a function of its fanout loading, input slew, supply voltage, operating tem- perature, and processing radiation tolerance. in a radiation environment, additional performa nce variances must be consid- ered. the ut0.6 ? crh ? array family simulation models account for all of these effects to accurate ly determine circuit performance for its particular set of use conditions. power dissipation each internal gate or i/o driv er has an average power consump- tion based on its switching frequency and capacitive loading. radiation-tolerant processes exhibit power dissipation that is typ- ical of cmos processes. for a rigorous power estimating methodology, refer to the aeroflex ut0.6 ? crh design manual or consult with an aerofl ex applications engineer. typical power dissipation 1.1 ? w/gate-mhz@5.0v 0.4 ? w/gate-mhz@3.3v
5 asic design software using a combination of state-of-the-art third-party and proprietary design tools, aeroflex delivers the cae support and capability to handle comp lex, high-performance asic designs from design concept through design verification and test. aeroflex?s flexible circuit creation methodology supports high level design by providing ut0.6 ? crh libraries for mentor graphics and synopsys synthesis tools. design verification is performed in any vhdl or verilog simulator or the mentor graphics environment, using aeroflex?s robust libraries. aeroflex also supports automatic test program generation to improve design testing. aeroflex hdl design system aeroflex offers a hardware description language (hdl) design system supporting vhdl and verilog. both the vhdl and verilog libraries provide sign-off quality models and robust tools. the vhdl libraries are vital 3.0 compliant, and the verilog libraries are ovi 1.0 compliant.with the library capabilities aeroflex provides, you can use high level design methods to synthesize your design for simulation. aeroflex also provides tools to verify that your hdl design will result in working asic devices. aeroflex?s hdl design system lets you easily access aeroflex?s radhard capabilities. advantages of the aeroflex hdl design system ? the aeroflex hdl design system gives you the freedom to use tools from synopsys, mentor graphics, cadence, and other vendors to help you synthesize and verify a design. ? aeroflex?s logic rules checker and tester rules checker allow you to verify partial or complete designs for compliance with aeroflex design rules. ? aeroflex hdl design system accepts back-annotation of timing information through sdf. ? your design stays entirely within the language in which you started (vhdl or verilog) preventing conversion headaches. xdt sm (external design translation) through aeroflex?s xdt servi ces, customers can convert an existing non-aeroflex design to aeroflex?s processes. the xdt tool is particularly useful for converting an fpga to an aeroflex radiation-tolerant ga te array. the xdt translation tools convert industry standard netlist formats and vendor libraries to aeroflex formats and libraries. industry standard netlist formats supported by aeroflex include: ? vhdl ? verilog hdl tm ? fpga source files (actel, altera, xilinx) ?edif ? third-party netlists supported by synopsys mentor modelsim hdl tool supplier completed asic design cadence nsim verilog xl vcs synopsys vss/vcs high level design activities aeroflex hdl design system aeroflex hdl design flow aeroflex gaisler ip
6 aeroflex mentor graphics design system the aeroflex mentor graphics design system software is fully integrated into the mentor graphics design environment, making it familiar and easy to use. aeroflex tools support mentor functions such as cross- highlighting, graphical menus, and design navigation. after creating a design in the me ntor graphics environment, you can easily verify the design for electrical rules compliance with the aeroflex logic rule s checker. testability can be verified with the aeroflex test er rules checker. both of these tools are fully integrated into the mentor graphics environment. when you have completed all design activities, aeroflex?s design transfer tool captures all the required files and prepares them for easy transfer to aeroflex . aeroflex uses this data to convert your design into a p ackaged and tested device. advantages of the aeroflex mentor design system ? aeroflex customers have succe ssfully used the aeroflex mentor graphics design sy stem for over a decade. ? aeroflex?s logic and tester rules checker tools allow you to verify partial or complete designs for compliance with aeroflex manufacturing practices and procedures. ? the design system accepts pre-and post-layout timing information to ensure your design results in devices that meet your specifications. ? the design system supports leonardo, and database transfer between synopsys and mentor. ? the design system supports powerful mentor graphics atpg capabilities. tools supported by aeroflex aeroflex supports libraries for: ? mentor graphics ? modelsim ?tessent ? synopsys ? design compiler ? primetime ? formality ?tetramax ? vital-compliant vhdl tools ? ovi-compliant verilog tools training and support aeroflex personnel conduct training classes tailored to meet individual needs. these classes can address a wide mix of engineering backgrounds and specific customer concerns. applications assistance is also available through all phases of asic design. design manufacturing aeroflex mentor design system translate an external design convert an fpga schematic entry synthesis design idea aeroflex mentor graphics design flow aeroflex gaisler ip
7 table 3. typical cell delays note: 1. all specifications in ns (typical). output load capacitance is 50pf. fanout loadi ng for input buffers and gates is the equiva lent of two gate input loads. cell output transition propagation delay 1 internal gates v dd = 5.0v v dd = 3.3v inv1, inverter hl .15 .16 lh .23 .29 inv4, inverter 4x hl .06 .07 lh .10 .16 nand2, 2-input nand hl .19 .25 lh .22 .33 nor2, 2-input nor hl .16 .22 lh .32 .45 dff - clk to q hl .81 1.12 lh .76 1.06 hl .75 1.05 lh .61 .85 output buffers oc5050n4, cmos hl 3.85 2.15 lh 4.66 3.76 ot5050n4, ttl, 4ma hl 5.58 5.49 lh 2.52 2.93 ot5050n12, ttl, 12ma hl 2.42 lh 1.29 input buffers ic5050, cmos hl .81 1.07 lh 1.16 1.18 it5050, ttl hl 1.39 1.12 lh 1.16 1.30
8 physical design using three layers of metal interconnect, aeroflex achieves optimized layouts that maximize sp eed of critical nets, overall chip performance, and design density up to 500,000 equivalent gates. test capability aeroflex supports all phases of test development from test stim- ulus generation through high-speed production test. this support includes atpg, fault simulation, and fault grading. scan design options are available on all ut0.6 ? crh storage ele- ments. automatic test program development capabilities handle large vector sets for use with ae roflex?s teradyne tiger tester supporting high-speed testing (up to 1.2ghz with pin multiplexing). unparalleled quality and reliability aeroflex is dedicated to meetin g the stringent performance re- quirements of aerospace and defense systems suppliers. aeroflex maintains the highest level of quality and reliability through our quality management program under mil-prf- 38535 and iso-9001. in 1988, we were the first gate array man- ufacturer to achieve qpl certifi cation and qualification of our technology families. our product assurance program has kept pace with the demands of cer tification and qualification. our quality management plan includes the following activities and initiatives. ? quality improvement plan ? failure analysis program ? spc plan ? corrective action plan ? change control program ? standard evaluation circ uit (sec) and technology charac- terization vehicle (tcv) assessment program ? certification and qualification program because of numerous product vari ations permitte d with custom- er specific designs, much of the reliability testing is performed using a standard evaluation circuit (sec) and technology characterization vehicl e (tcv). the tcv utilizes test struc- tures to evaluate hot carrier ag ing, electromigration, and time dependent test samples for reliability testing. data from the wa- fer-level testing can provide rapid feedback to the fabrication process, as well as establish th e reliability performance of the product before it is packaged and shipped. radiation tolerance aeroflex incorporates radiation- tolerance techniques in process design, design rules, array design, power distribution, and li- brary element design. all key radiation-tolerance process parameters are controlled and mo nitored using statistical meth- ods and in-line testing. notes: 1. total dose co-60 testing is in accordance with mil-std-883, method 1019. data sheet electrical characteristics guaranteed to 1.0e 5 rads(si o 2 ). all post-radiation values measured at 25 ? c. 2. total dose co-60 testing is in accordance with mil-std-883, method 1019 at dose rates <1 rad(si o 2 )/s. 3. short pulse 20ns fwhm (full width, half maximum). 4. is design dependent; seu limit based on standard evaluation circuit at 4.5v worst case condition. 5. seu-hard flip-flop cell. non- hard flip-flop typical is 4e -8 . parameter radiation tolerance notes total dose 1.0e 5 rad(sio 2 ) 3.0e 5 rad(sio 2 ) 1 2 dose rate upset 1.0e 8 rad(si)/sec 3 dose rate survivability 1.0e 11 rad(si)/sec 4 seu <2.0e -10 errors per cell-day 4, 5 projected neutron fluence 1.0e 14 n/sq cm latchup latchup-immune over speci- fied use conditions
9 absolute maximum ratings 1 (referenced to v ss ) note: 1. stresses outside the listed absolute maxi mum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any othe r conditions beyond limits indi cated in the operational sec tions of this specification i s not recommended. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions symbol parameter limits v dd dc supply voltage -0.3 to 6.0v v i/o voltage on any pin -0.3v to v dd + 0.3 t stg storage temperature -65 to +150 ? c t j maximum junction temperature +175 ? c i lu latchup immunity ? 150ma i i dc input current ? 10ma t ls lead temperature (soldering 5 sec) +300 ? c symbol parameter limits v dd positive supply voltage 3.0 to 5.5v t c case temperature range -55 to +125c v in dc input voltage 0v to v dd
10 5v dc electrical characteristics (v dd = 5.0v ? 10%; -55 ? c < t c < +125 ? c) 1,2 symbol parameter condition min typ max unit v il 3 low-level input voltage ttl inputs cmos v dd = 4.5v and 5.5v 0.8 .3v dd v v ih 3 high-level input voltage ttl inputs cmos v dd = 4.5v and 5.5v 2.2 .7v dd v v t + 3 schmitt trigger, positive going threshold v dd = 4.5v and 5.5v .2.4 7v dd v v t - 3 schmitt trigger, negative going threshold v dd = 4.5v and 5.5v 0.9 .3v dd v v h 4 schmitt trigger, typical range of hysteresis 0.4 0.6 v i in input leakage current ttl, cmos, and schmitt inputs inputs with pull-down resistors inputs with pull-down resistors inputs with pull-up resistors inputs with pull-up resistors cold spare inputs - normal mode cold spare inputs - cold spare mode v dd = 5.5v v in = v dd and v ss v in = v dd v in = v ss v in = v ss v in = v dd v in = 0 to 5.5v v dd = v ss = 0v v in = v and 5.5v -1 +20 -5 -225 -5 -5 -5 1 +225 +5 -20 +5 +5 +5 ? a v ol low-level output voltage ttl 2.0ma buffer ttl 4.0ma buffer ttl 8.0ma buffer ttl 12.0ma buffer * cmos outputs cmos outputs (optional) cmos outputs (cold spare) v dd = 4.5v i ol = 2.0ma i ol = 4.0ma i ol = 8.0ma i ol = 12.0ma i ol = 1.0 ? a i ol = 100 ? a i ol = 100 ? a 0.4 0.4 0.4 0.4 0.05 0.25 0.25 v v oh high-level output voltage ttl 2.0ma buffer ttl 4.0ma buffer ttl 8.0ma buffer ttl 12.0ma buffer * cmos outputs cmos outputs (optional) cmos outputs (cold spare) v dd = 4.5v i oh = -2.0ma i oh = -4.0ma i oh = -8.0ma i oh = -12.0ma i oh = -1.0 ? a i oh = -100 ? a i oh = -100 ? a 2.4 2.4 2.4 2.4 v dd -0.05 v dd -0.35 v dd -0.35 v
11 notes: * contact aeroflex prior to usage. 1. these devices are capable of being config ured and support dual voltage: 3.3v and/or 5.0v bus, 2.5v core/3.3v or 5.0v core/5. 0v bus. the supply voltage range shall be specified in the aid. 2. devices are supplied to this drawing will meet all levels m, d, p, l, r and f of irradiation. however, this device is only t ested at the "r" and "f" level. pre and post irradiation values are identical unless otherw ise specified in table 1. when performing post irradiation electrical measurement s for any rha level, t a = +25 o c. symbol parameter condition min typ max unit i oz three-state output leakage current ttl 2.0ma buffer ttl 4.0ma buffer, cmos ttl 8.0ma buffer ttl 12.0ma buffer * cold spare inputs - normal mode cold spare inputs - cold spare mode v dd = 5.5v v o = 0v and 5.5v v dd = v ss = 0 v dd = 0 to 5.5v -5 -10 -20 -30 -5 -5 5 10 20 30 -5 -5 ? a i os 4,5 short-circuit output current ttl 2.0ma buffer ttl 4.0ma buffer, cmos ttl 8.0ma buffer ttl 12.0ma buffer * v o = 0v and 5.5v -50 -100 -200 -300 50 100 200 300 ma i ddq quiescent supply current 6 group a subgroups 1,3 v dd = 5.5v 200k gates 400k gates 500k gates 50 100 180 ? a group a subgroup 2 v dd = 5.5v 200k gates 400k gates 500k gates 1 2 3 ma group a, subgroup 1 rha designator: m, d, p, l, r,f v dd = 5.5v 200k gates 400k gates 500k gates 4 8 12 ma c in 7 input capacitance ? 23 pf c out 7 output capacitance ttl 2.0ma buffer ttl 4.0ma buffer, cmos ttl 8.0ma buffer ttl 12.0ma buffer * ? 22 26 26 26 pf c io 7 bidirect i/o capacitance ttl 4.0ma buffer, cmos ttl 8.0ma buffer ttl 12.0ma buffer * ? 24 26 26 pf
12 3. functional tests are conducted in accordance with mil-std-88 3 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, fo r ttl, cmos, or schmitt compatible inputs. de vices may be tested using any input volt age within the above specified ra nge, but are guaranteed to v ih (min) and v il (max). 4. supplied as a design limit bu t not guaranteed or tested. 5. not more than one output may be shorted at a time for maximum duration of one second. 6. all inputs with internal pull-ups should be left floating. all other inputs should be tied high or low. 7. capacitance measured for initial qualificatio n and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz @0v and a signal amplitude of < 50mv rms.
13 3v dc electrical characteristics (v dd = 3.3v ? .3v; -55 ? c < t c < +125 ? c) 1,2 symbol parameter condition min typ max unit v il 3 low-level input voltage cmos v dd = 3.0v and 3.6v 0.8 .3v dd v v ih 3 high-level input voltage cmos v dd = 3.0v and 3.6v 2.4 .7v dd v v t + 3 schmitt trigger, positive going threshold v dd = 3.0v and 3.6v .7v dd v v t - 3 schmitt trigger, negative going t hreshold v dd = 3.0v and 3.6v .3v dd v v h 4 schmitt trigger, typical range of hysteresis .6 v i in input leakage current ttl, cmos, and schmitt inputs inputs with pull-down resistors inputs with pull-down resistors inputs with pull-up resistors inputs with pull-up resistors cold spare inputs - normal mode cold spare inputs - cold spare mode v dd = 3.6v v in = v dd and v ss v in = v dd v in = v ss v in = v ss v in = v dd v in = 0 to 3.6v v dd = v ss = 0v v in = v and 3.6v -1 +10 -5 -225 -5 -5 -5 1 +225 +5 -10 +5 +5 +5 ? a v ol low-level output voltage ttl 2.0ma buffer ttl 4.0ma buffer ttl 8.0ma buffer cmos outputs cmos outputs (optional) cmos outputs (cold spare) v dd = 3.0v i ol = 2.0ma i ol = 4.0ma i ol = 8.0ma i ol = 1.0 ? a i ol = 100 ? a i ol = 100 ? a 0.4 0.4 0.4 0.05 0.25 0.25 v v oh high-level output voltage ttl 2.0ma buffer ttl 4.0ma buffer, cmos ttl 8.0ma buffer cmos outputs cmos outputs (optional) cmos outputs (cold spare) v dd = 3.0v i oh = 2.0ma i oh = 2.0ma i oh = 8.0ma i oh = 1.0 ? a i oh = 100 ? a i oh = 100 ? a 2.4 2.4 2.4 v dd -0.05 v dd -0.35 v dd -0.35 v
14 notes: * contact aeroflex prior to usage. 1. these devices are capable of being config ured and support dual voltage: 3.3v and/or 5.0v bus, 2.5v core/3.3v or 5.0v core/5. 0v bus. the supply voltage range shall be specified in the aid. 2. devices are supplied to this drawing will meet all levels m, d, p, l, r and f of irradiation. however, this device is only t ested at the "r" and "f" level. pre and post irradiation values are identical unless otherw ise specified in table 1. when performing post irradiation electrical measurement s for any rha level, t a = +25 o c. 3. functional tests are conducted in accordance with mil-std-88 3 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, fo r ttl, cmos, or schmitt compatible inputs. de vices may be tested using any input volt age within the above specified ra nge, but are guaranteed to v ih (min) and v il (max). 4. supplied as a design limit bu t not guaranteed or tested. 5. not more than one output may be shorted at a time for maximum duration of one second. 6. all inputs with internal pull-ups should be left floating. all other inputs should be tied high or low. 7. capacitance measured for initial qualificatio n and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz @0v and a signal amplitude of < 50mv rms. symbol parameter condition min typ max unit i oz three-state output leakage current cmos cold spare inputs - normal mode cold spare inputs - cold spare mode v dd = 3.6v v o = v dd and v ss v dd = v ss = 0v v o = 0v and 3.6v -20 -5 -5 20 5 5 ? a i os 4,5 short-circuit output current 5 cmos, lvttl v o = v dd and v ss -200 200 ma i ddq quiescent supply current 6 group a subgroups 1,3 v dd = 5.5v 200k gates 400k gates 500k gates 50 100 180 ? a group a subgroup 2 v dd = 5.5v 200k gates 400k gates 500k gates 1 2 3 ma group a, subgroup 1 rha designator: m, d, p, l, r v dd = 5.5v 200k gates 400k gates 500k gates 4 8 12 ma c in 7 input capacitance ? 23 pf c out 7 output capacitance cmos ? 26 pf c io 7 bidirect i/o capacitance cmos ? 26 pf
15 intel is a registered trad emark of intel corporation mentor, mentor graphics, autologic ii, quic ksim ii, quickfault ii, quickhdl, quickgrade ii, fastscan, flextest and dft advisor are registered trademarks of mentor graphics corporation sun is a registered trademark of sun microsystems, inc. verilog and leapfrog are registered trad emarks of cadence design systems, inc. synopsys, design compiler, test compiler plus, vhdl compiler, ver ilog hdl compiler, testsim and vss are trademarks of synopsys, inc. vantage is a trademark of viewlogic
16 www.aeroflex.com info-ams@aeroflex.com our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused aeroflex colorado springs, inc., reserves the right to make changes to any products and services described herein at any time without notice. consult aeroflex or an authorized sales representa tive to verify that the information in this data sheet is current before using this product. aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, ex cept as expressly agreed to in writing by aeroflex; nor does the purchase, lease, or use of a product or service fro m aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of aeroflex or of third parties. this product is controlled for export under the internat ional traffic in arms regulations (i tar). a license from the u.s. gov- ernment is required prior to the export of this product from the united states. aeroflex colorado spring s - datasheet definition advanced datasheet - product in development preliminary datasheet - shipping prototype datasheet - shipping qml & reduced hirel

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